------------------------------------------------------------------------
-- 8x8->16-bit unsigned sequential radix-4 multiplier
--   2 bits at a time calculation; no start/ready signals
--   behavioral-RTL style, OK for Xilinx ISE (10.1)
-- L(R)V - 2009
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity multiplier2 is
  port ( clk: in bit;
         a, b: in unsigned(7 downto 0);
         c: out unsigned(15 downto 0) );
end entity multiplier2;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture bhv_rtl of multiplier2 is
begin
  process
    variable a_bf, b_bf: unsigned(7 downto 0);
    variable c_bf: unsigned(15 downto 0);
    variable prev: std_logic;
    procedure mul_2bits ( variable a: in unsigned(7 downto 0);
                          variable b: inout unsigned(7 downto 0);
                          variable c: inout unsigned(15 downto 0);
                          variable prv: inout std_logic ) is
      variable b_bits: std_logic_vector(2 downto 0);
    begin
      b_bits := prv & std_logic_vector(b(1 downto 0));
      case b_bits is
      when "000" =>  prv := '0';  c := c;
      when "001" =>  prv := '0';  c := c + (a & "00000000");
      when "010" =>  prv := '0';  c := c + (a(6 downto 0) & "000000000");
      when "011" =>  prv := '1';  c := c - (a & "00000000");
      when "100" =>  prv := '0';  c := c + (a & "00000000");
      when "101" =>  prv := '0';  c := c + (a(6 downto 0) & "000000000");
      when "110" =>  prv := '1';  c := c - (a & "00000000");
      when others => prv := '1';  c := c;
      end case; 
      b := "00" & b(7 downto 2);    c := "00" & c(15 downto 2);
    end procedure mul_2bits;
  begin
    wait on clk until clk='1';
    a_bf := a;  b_bf := b;  c_bf := (others=>'0');  prev := '0';
    wait on clk until clk='1';
    mul_2bits(a_bf,b_bf,c_bf,prev);    wait on clk until clk='1';
    mul_2bits(a_bf,b_bf,c_bf,prev);    wait on clk until clk='1';
    mul_2bits(a_bf,b_bf,c_bf,prev);    wait on clk until clk='1';
    mul_2bits(a_bf,b_bf,c_bf,prev);    wait on clk until clk='1';
    c <= c_bf;
  end process;

end architecture bhv_rtl;