------------------------------------------------------------------------
-- 16x16->32-bit unsigned sequential radix-2 multiplier
--   bit-by-bit calculation; behavioral-RTL style
-- Clock, start & stop signals added to use with
--   the adapted GCD testbench
-- L(R)V - 2025
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity multiplier is
  port ( xi, yi: in unsigned(15 downto 0);
         rst    : in std_logic;
         xo     : out unsigned(31 downto 0);
         rdy    : out std_logic;
         clk    : in std_logic);
end entity multiplier;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture bhv_rtl of multiplier is
begin
  process
    variable a_bf, b_bf: unsigned(15 downto 0);
    variable c_bf: unsigned(31 downto 0);
    procedure mul_bit ( variable a: in unsigned(15 downto 0);
                        variable b: inout unsigned(15 downto 0);
                        variable c: inout unsigned(31 downto 0) ) is
    begin
      if  b(0)='1'  then    c := c + (a & "0000000000000000");    end if;
      b := '0' & b(15 downto 1);    c := '0' & c(31 downto 1);
    end procedure mul_bit;
  begin
    -- Wait for the new input data
    wait on clk until clk='1' and rst='0';

    a_bf := xi;  b_bf := yi;  c_bf := (others=>'0');  rdy <= '0';
    wait on clk until clk='1';

    -- Calculate
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';

    -- Ready
    xo <= c_bf;    rdy <= '1';
    wait on clk until clk='1';
  end process;

end architecture bhv_rtl;