------------------------------------------------------------------------
-- 16x16->32-bit unsigned combinational multiplier
-- Clock, start & stop signals added to use with
--   the adapted GCD testbench
-- L(R)V - 2025
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity multiplier is
  port ( xi, yi: in unsigned(15 downto 0);
         rst    : in std_logic;
         xo     : out unsigned(31 downto 0);
         rdy    : out std_logic;
         clk    : in std_logic);
end entity multiplier;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture combi of multiplier is
  signal a, b: unsigned(15 downto 0);
begin
  process
    variable c_bf: unsigned(31 downto 0);
  begin
    -- Wait for the new input data
    wait on clk until clk='1' and rst='0';

    a <= xi;    b <= yi;    rdy <= '0';
    wait on clk until clk='1';

    -- Calculate
    c_bf := a * b;
    -- wait on clk until clk='1';

    -- Ready
    xo <= c_bf;    rdy <= '1';
    wait on clk until clk='1';
  end process;

end architecture combi;