------------------------------------------------------------------------
-- Testbench for multiplier implementations.
-- Adapted from the GCD testbench.
------------------------------------------------------------------------
-- L(R)V 2025
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test is
end test;

architecture bench of test is
  signal clk, rst, rdy, hlt: std_logic := '1';
  signal x, y: unsigned(15 downto 0);
  signal res: unsigned(31 downto 0);

  component multiplier
    port (xi, yi : in unsigned(15 downto 0);
          rst    : in std_logic;
          xo     : out unsigned(31 downto 0);
          rdy    : out std_logic;
          clk    : in std_logic);
  end component;
begin
  clk <= not clk after 10 ns when hlt='1';

  U1: multiplier port map (x, y, rst, res, rdy, clk);

  process
    type int_array is array (0 to 3) of integer;
    constant a: int_array := ( 27,   33,   245,    52);
    constant b: int_array := ( 18,  256,    45,   452);
    -- expected results       486, 8448, 11025, 23504
  begin
    wait on clk until clk='0';
    for  i in a'range  loop
      x <= conv_unsigned(a(i),16);
      y <= conv_unsigned(b(i),16);
      rst <= '0';
      wait on clk until clk='0';
      rst <= '1';
      --wait on clk until clk='0';
      while  rdy = '0'  loop
        wait on clk until clk='0';
      end loop;
      wait on clk until clk='0';
    end loop;
    wait on clk until clk='0';
    hlt <= '0';    wait;
  end process;
end bench;