------------------------------------------------------------------------
-- 8x8->16-bit unsigned sequential radix-2 multiplier
--   bit-by-bit calculation; no start/ready signals
--   behavioral-RTL style, OK for Xilinx ISE (10.1)
-- L(R)V - 2009
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity multiplier is
  port ( clk: in bit;
         a, b: in unsigned(7 downto 0);
         c: out unsigned(15 downto 0) );
end entity multiplier;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture bhv_rtl of multiplier is
begin
  process
    variable a_bf, b_bf: unsigned(7 downto 0);
    variable c_bf: unsigned(15 downto 0);
    procedure mul_bit ( variable a: in unsigned(7 downto 0);
                        variable b: inout unsigned(7 downto 0);
                        variable c: inout unsigned(15 downto 0) ) is
    begin
      if  b(0)='1'  then    c := c + (a & "00000000");    end if;
      b := '0' & b(7 downto 1);    c := '0' & c(15 downto 1);
    end procedure mul_bit;
  begin
    wait on clk until clk='1';
    a_bf := a;  b_bf := b;  c_bf := (others=>'0');
    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    mul_bit(a_bf,b_bf,c_bf);    wait on clk until clk='1';
    c <= c_bf;
  end process;

end architecture bhv_rtl;