library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity multiplier0 is
  port ( clk: in bit;
         a, b: in unsigned(7 downto 0);
         c: out unsigned(15 downto 0) );
end entity multiplier0;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture rtl of multiplier0 is
begin
  process
    variable c_bf: unsigned(15 downto 0);
  begin
    wait on clk until clk='1';
    c_bf := a * b;
    c <= c_bf;
  end process;

end architecture rtl;