library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity decoder is
  port ( c3, c2, c1, c0: in std_logic;
         led_a, led_b, led_c, led_d,
           led_e, led_f, led_g: out std_logic );
end decoder;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

architecture behave of decoder is
  signal sw: std_logic_vector(3 downto 0);
  signal led: std_logic_vector(0 to 6);
begin
  sw <= c3 & c2 & c1 & c0;
  process (sw) begin
    case sw is
    when "0000" =>  led <= "1110111";
    when "0001" =>  led <= "0010010";
    when "0010" =>  led <= "1011101";
    when "0011" =>  led <= "1011011";
    when "0100" =>  led <= "0111010";
    when "0101" =>  led <= "1101011";
    when "0110" =>  led <= "1101111";
    when "0111" =>  led <= "1010010";
    when "1000" =>  led <= "1111111";
    when "1001" =>  led <= "1111011";
    when "1010" =>  led <= "1111110";
    when "1011" =>  led <= "0101111";
    when "1100" =>  led <= "1100101";
    when "1101" =>  led <= "0011111";
    when "1110" =>  led <= "1101101";
    when others =>  led <= "1101100";
    end case;
  end process;
  led_a <= led(0);  led_b <= led(1);  led_c <= led(2);
  led_d <= led(3);  led_e <= led(4);  led_f <= led(5);
  led_g <= led(6);
end behave;