------------------------------------------------------------------------
-- IAY0105 - Homework #1. Test bench for the example task.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2010 - Tallinn
------------------------------------------------------------------------
library IEEE; use IEEE.std_logic_1164.all;
entity test2 is
end entity test2;

library IEEE; use IEEE.std_logic_1164.all;
architecture bench of test2 is
  signal a, b, c, d, k, l, m, n: std_logic;
  signal k2, k3, l2, l3, m2, m3, n2, n3: std_logic;
  component f_system
    port ( a, b, c, d: in std_logic;
           k, l, m, n: out std_logic );
  end component;
  for U1: f_system use entity work.f_system(tabel);
  for U2: f_system use entity work.f_system(espresso);
  for U3: f_system use entity work.f_system(opti);
begin
  -- Input signaals (after every 10 ns)
  a <= '0' after 0 ns, '1' after 80 ns, '0' after 160 ns;
  b <= '0' after 0 ns, '1' after 40 ns, '0' after 80 ns, '1' after 120 ns;
  c <= '0' after 0 ns, '1' after 20 ns, '0' after 40 ns, '1' after 60 ns,
       '0' after 80 ns, '1' after 100 ns, '0' after 120 ns, '1' after 140 ns;
  d <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns,
       '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns,
       '0' after 80 ns, '1' after 90 ns, '0' after 100 ns, '1' after 110 ns,
       '0' after 120 ns, '1' after 130 ns, '0' after 140 ns, '1' after 150 ns;

  -- System of Boolean functions
  U1: f_system port map (a, b, c, d, k, l, m, n);
  U2: f_system port map (a, b, c, d, k2, l2, m2, n2);
  U3: f_system port map (a, b, c, d, k3, l3, m3, n3);
end architecture bench;