//----------------------------------------------------------------------
// IAS0150 - Homework #2. Test bench for the example task.
//----------------------------------------------------------------------
// (C) Peeter Ellervee - 2026 - Tallinn
//----------------------------------------------------------------------

`timescale 1 ns / 1 ns

module test_bench;
  logic [1:4] xi = 0;
  wire y1a, y1b, y1c, y1x;
  wire y2a, y2b, y2c, y2x;
  wire y3a, y3b, y3c, y3x;
  wire y4a, y4b, y4c, y4x;

  // Sequence 0000 ... 1111
  initial begin
    repeat (16) #10 xi++;
    $stop;
  end

  // Truth table
  fs_table u1 (xi[1], xi[2], xi[3], xi[4], y1a, y2a, y3a, y4a);
  assign y1x=y1a, y2x=y2a, y3x=y3a, y4x=y4a;

  // Espresso result
  fs_espresso u2 (xi[1], xi[2], xi[3], xi[4], y1b, y2b, y3b, y4b);
  assign y1x=y1b, y2x=y2b, y3x=y3b, y4x=y4b;

  // Optimized circuit
  fs_opti u3 (xi[1], xi[2], xi[3], xi[4], y1c, y2c, y3c, y4c);
  assign y1x=y1c, y2x=y2c, y3x=y3c, y4x=y4c;

endmodule