------------------------------------------------------------------------
-- IAY0105 - Homework #1. Optimized description of the example task.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2010 - Tallinn
------------------------------------------------------------------------
library IEEE; use IEEE.std_logic_1164.all;
entity f_system is
  port ( a, b, c, d: in std_logic;
         k, l, m, n: out std_logic );
end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal ai, bi, ci, di: std_logic;
  signal t0i, t2i, t4i, t6x, t6i, t7i, t9i: std_logic;
  signal t51, t52, t53i, t54, t1t8i, t3t6i, t5t6i: std_logic;
begin
  ai <= not (a and a);          bi <= not (b and b);
  ci <= not (c and c);          di <= not (d and d);

  t0i <= a or d;                t2i <= not (ai and c);
  t4i <= not (a and c and d);   t6x <= not (c or d);
  t6i <= not (b and t6x);       t7i <= not (b and d);
  t9i <= not (bi and c);

  t51 <= not (a and d);         t52 <= b xor d;
  t53i <= not (a and bi);       t54 <= not (t2i and t53i);

  t1t8i <= not (di and t54);    t3t6i <= not (t52 and ci);
  t5t6i <= not (t51 and b and ci);

  k <= not (t0i and t4i and t5t6i);
  l <= not (t2i and t3t6i);
  m <= not (t1t8i and t6i and t7i);
  n <= not (t1t8i and t4i and t9i);
end architecture opti;