------------------------------------------------------------------------
-- IAY0105 - Homework #1. Espresso result of the example task.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2010 - Tallinn
------------------------------------------------------------------------
library IEEE; use IEEE.std_logic_1164.all;
entity f_system is
  port ( a, b, c, d: in std_logic;
         k, l, m, n: out std_logic );
end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture espresso of f_system is
begin
  k <= ((not a) and (not d)) or (a and c and d) or
       ((not a) and b and (not c)) or (b and (not c) and (not d));
  l <= ((not a) and c) or ((not b) and (not c) and d) or
       (b and (not c) and (not d));
  m <= ((not a) and c and (not d)) or (b and (not c) and (not d)) or
       (b and d) or (a and (not b) and (not d));
  n <= ((not a) and c and (not d)) or (a and c and d) or
       (a and (not b) and (not d)) or ((not b) and c);
end architecture espresso;