------------------------------------------------------------------------
-- IAY0150 - Homework #1. Example task - #1, gates & delays, optimized.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2016 - Tallinn
------------------------------------------------------------------------
library IEEE; use IEEE.std_logic_1164.all;
entity f_system is
  port ( x1, x2, x3, x4: in std_logic;
         y1, y2, y3, y4: out std_logic );
end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal x1i, x2i, t1i, t2i, t3x, t3i, t4i, t5i, t6: std_logic;
  signal t7, t8x, t8, t68i, t9i, t19, t197i: std_logic;

  component and2 is
    port (a,b: in std_logic; o: out std_logic); end component;
  component or3 is
    port (a,b,c: in std_logic; o: out std_logic); end component;
  component nand2 is
    port (a,b: in std_logic; o: out std_logic); end component;
  component nand3 is
    port (a,b,c: in std_logic; o: out std_logic); end component;
  component nor2 is
    port (a,b: in std_logic; o: out std_logic); end component;
begin
  u_x1i: nand2 port map (x1,x1,x1i);
  u_x2i: nand2 port map (x2,x2,x2i);

  u_t1i: or3 port map (t4i,x1,x3,t1i);
  u_t2i: nand3 port map (x1,x3,x4,t2i);
  u_t3x: nor2 port map (x3,x4,t3x);
  u_t3i: nand2 port map (x2,t3x,t3i);
  u_t4i: nand2 port map (x2,x4,t4i);
  u_t5i: nand2 port map (x2i,x3,t5i);
  u_t6: and2 port map (t7,x3,t6);
  u_t7: nor2 port map (x1,x4,t7);
  u_t8x: nor2 port map (x2,x4,t8x);
  u_t8: and2 port map (x1,t8x,t8);
  u_t68i: nor2 port map (t6,t8,t68i);
  u_t9i: nand2 port map (x1,x3,t9i);
  u_t19: nand2 port map (t1i,t9i,t19);
  u_t197i: nor2 port map (t19,t7,t197i);

  u_y1: nand2 port map (t197i,t3i,y1);
  u_y2: nor2 port map (t19,t8,y2);
  u_y3: nand3 port map (t3i,t4i,t68i,y3);
  u_y4: nand3 port map (t2i,t5i,t68i,y4);
end architecture opti;