------------------------------------------------------------------------
-- IAS0150 - Homework #1. Example task - #2, gates, kernels, no optimization.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2022/2023 - Tallinn
------------------------------------------------------------------------
-- library IEEE; use IEEE.std_logic_1164.all;
-- entity f_system is
--   port ( x1, x2, x3, x4: in std_logic;
--          y1, y2, y3, y4: out std_logic );
-- end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal x1i, x2i, x3i, x4i: std_logic;
--  signal t1a, t1b, t1c, t1d, t2a, t2b, t2c: std_logic;
  signal t1a, t1b, t1bi, t1ci, t1dx, t1di, t2a, t2b, t2ci: std_logic;
--  signal t3a, t3b, t5, t6, t7, t8, t9: std_logic;
  signal t3a, t3bi, t5i, t6i, t7, t7i, t8a, t8i, t9i: std_logic;
begin
--  x1i <= not x1;
  x1i <= not (x1 and x1);
--  x2i <= not x2;
  x2i <= not (x2 and x2);
--  x3i <= not x3;
  x3i <= not (x3 and x3);
--  x4i <= not x4;
  x4i <= not (x4 and x4);

--  t1a <= x1i or x4i;
  t1a <= not (x1 and x4);


--  t1c <= t1b and t1a;
  t1ci <= not (t1b and t1a);
  t1b <= x2  and x3i;                --1--
--  t1bi <= not (x2  and x3i);         --2--
--  t1b  <= not (t1bi and t1bi);       --2--
--  t1b  <= not (x2i or x3);           --3--
--  t1bi <= not (t1b and t1b);         --3--
--  t1d <= t1b and x1i and x4;
  t1di <= not (t1b and x1i and x4);  --1--
--  t1dx <= not (t1bi or x1);          --2&3--
--  t1di <= not (t1dx and x4);         --2&3--

  t2a <= x1 xor x4;            --1--
  t2b <= not (t2a and t2a);    --1--
--  t2b <= x1i xor x4;           --2--
--  t2b <= x1 xor x4i;           --3--
--  t2c <= x3  and t2b;
  t2ci <= not (x3 and t2b);

  t3a <= x3i or x4;         --1--
--  t3a <= not (x3 and x4i);  --2--
--  t3b <= x2  and t3a;
  t3bi <= not (x2  and t3a);

--  t5  <= x2i and x3;
  t5i <= not (x2i and x3);

--  t6  <= x3  and t7;
  t6i <= x3i or t7i;        --1--
--  t7  <= not t7i;           --2--
--  t6i <= not (x3  and t7);  --2--

--  t7  <= x1i and x4i;
  t7i <= not (x1i and x4i);  --1--
--  t7i <= x1 or x4;  --2--

--  t8  <= x1  and x2i and x4i;
  t8i <= not (x1 and x2i and x4i);  --1--
--  t8a <= not (x2 or x4);     --2--
--  t8i <= not (x1  and t8a);  --2--

--  t9  <= x1  and x3;
  t9i <= not (x1 and x3);

--  y1  <= t1c or t7 or t9;
  y1  <= not (t1ci and t7i and t9i);
--  y2  <= not (t1d or t8 or t9i);
  y2  <= t1di and t8i and t9i;
--  y3  <= t3b or t6 or t8;
  y3  <= not (t3bi and t6i and t8i);
--  y4  <= t2c or t5 or t8;
  y4  <= not (t2ci and t5i and t8i);
end architecture opti;