------------------------------------------------------------------------
-- IAS0150 - Homework #1. Example task - #2, gates, kernels, optimized.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2022/2023 - Tallinn
------------------------------------------------------------------------
-- library IEEE; use IEEE.std_logic_1164.all;
-- entity f_system is
--   port ( x1, x2, x3, x4: in std_logic;
--          y1, y2, y3, y4: out std_logic );
-- end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal x1i, x2i, x3i, x4i: std_logic;
  signal t1a, t1b, t1ci, t1di, t2b, t2ci: std_logic;
  signal t3a, t3bi, t5i, t6i, t7i, t8i, t9i: std_logic;
begin
  x1i <= not (x1 and x1);
  x2i <= not (x2 and x2);
  x3i <= not (x3 and x3);
  x4i <= not (x4 and x4);

  t1a <= not (x1 and x4);
  t1b <= x2 and x3i;
  t1ci <= not (t1b and t1a);
  t1di <= not (t1b and x1i and x4);
  t2b <= x1i xor x4;
  t2ci <= not (x3 and t2b);
  t3a <= not (x3 and x4i);
  t3bi <= not (x2  and t3a);
  t5i <= not (x2i and x3);
  t6i <= x3i or t7i;
  t7i <= not (x1i and x4i);
  t8i <= not (x1 and x2i and x4i);
  t9i <= not (x1 and x3);

  y1  <= not (t1ci and t7i and t9i);
  y2  <= t1di and t8i and t9i;
  y3  <= not (t3bi and t6i and t8i);
  y4  <= not (t2ci and t5i and t8i);
end architecture opti;