------------------------------------------------------------------------
-- IAY0150 - Homework #1. Example task - #2, gates, kernels, no optimization.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2016/2023 - Tallinn
------------------------------------------------------------------------
-- library IEEE; use IEEE.std_logic_1164.all;
-- entity f_system is
--   port ( x1, x2, x3, x4: in std_logic;
--          y1, y2, y3, y4: out std_logic );
-- end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal x1i, x2i, x3i, x4i: std_logic;
  signal t1a, t1b, t1c, t1d, t2a, t2b, t2c: std_logic;
  signal t3a, t3b, t5, t6, t7, t8, t9: std_logic;
begin
  x1i <= not x1;
  x2i <= not x2;
  x3i <= not x3;
  x4i <= not x4;

  t1a <= x1i or x4i;
  t1b <= x2  and x3i;
  t1c <= t1b and t1a;
  t1d <= t1b and x1i and x4;
  t2a <= x1 xor x4;
  t2b <= not t2a;
  t2c <= x3  and t2b;
  t3a <= x3i or x4;
  t3b <= x2  and t3a;
  t5  <= x2i and x3;
  t6  <= x3  and t7;
  t7  <= x1i and x4i;
  t8  <= x1  and x2i and x4i;
  t9  <= x1  and x3;

  y1  <= t1c or t7 or t9;
  y2  <= not (t1d or t8 or t9);
  y3  <= t3b or t6 or t8;
  y4  <= t2c or t5 or t8;
end architecture opti;