------------------------------------------------------------------------
-- IAY0150 - Homework #1. Example task - #1, gates, no optimization.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2016/2023 - Tallinn
------------------------------------------------------------------------
-- library IEEE; use IEEE.std_logic_1164.all;
-- entity f_system is
--   port ( x1, x2, x3, x4: in std_logic;
--          y1, y2, y3, y4: out std_logic );
-- end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal x1i, x2i, x3i, x4i: std_logic;
--signal t1, t2, t3, t4, t5, t6, t7, t8, t9: std_logic;
  signal t1, t2i, t3, t4, t5i, t6, t7, t8, t9: std_logic;
--signal t19, t68: std_logic;
  signal t19, t68i: std_logic;
begin
  x1i <= not x1;
  x2i <= not x2;
  x3i <= not x3;
  x4i <= not x4;

  t1 <= t4  and x1i and x3i;
--t2 <= x1  and x3  and x4;
  t2i <= not (x1 and x3 and x4);
  t3 <= x2  and x3i and x4i;
  t4 <= x2  and x4;
--t5 <= x2i and x3;
  t5i <= not (x2i and x3);
  t6 <= t7  and x3;
  t7 <= x1i and x4i;
  t8 <= x1  and x2i and x4i;
  t9 <= x1  and x3;

  t19 <= t1 or t9;
--t68 <= t6 or t8;
  t68i <= not (t6 or t8);

  y1 <= t19 or t3 or t7;
  y2 <= not (t19 or t8);
--y3 <= t3 or t4 or t68;
  y3 <= t3 or t4 or (not t68i);
--y4 <= t2 or t5 or t68;
  y4 <= not (t2i and t5i and t68i);
end architecture opti;