------------------------------------------------------------------------
-- IAY0150 - Homework #1. Example task - into gates, step #1.
------------------------------------------------------------------------
-- (C) Peeter Ellervee - 2016/2023 - Tallinn
------------------------------------------------------------------------
-- library IEEE; use IEEE.std_logic_1164.all;
-- entity f_system is
--   port ( x1, x2, x3, x4: in std_logic;
--          y1, y2, y3, y4: out std_logic );
-- end entity f_system;

library IEEE; use IEEE.std_logic_1164.all;
architecture opti of f_system is
  signal t1, t2, t3, t4, t5, t6, t7, t8, t9: std_logic;
  signal t19, t68: std_logic;
begin
--t1 <= (not x1) and x2 and (not x3) and x4;
  t1 <= t4 and (not x1) and (not x3);
  t2 <= x1 and x3 and x4;
  t3 <= x2 and (not x3) and (not x4);
  t4 <= x2 and x4;
  t5 <= (not x2) and x3;
--t6 <= (not x1) and x3 and (not x4);
  t6 <= t7 and x3;
  t7 <= (not x1) and (not x4);
  t8 <= x1 and (not x2) and (not x4);
  t9 <= x1 and x3;

  t19 <= t1 or t9;
  t68 <= t6 or t8;

--y1 <= t1 or t3 or t7 or t9;
  y1 <= t19 or t3 or t7;
--y2 <= not (t1 or t8 or t9);
  y2 <= not (t19 or t8);
--y3 <= t3 or t4 or t6 or t8;
  y3 <= t3 or t4 or t68;
--y4 <= t2 or t5 or t6 or t8;
  y4 <= t2 or t5 or t68;
end architecture opti;