entity  fsm_test_both  is
end entity fsm_test_both;

architecture  bench  of  fsm_test_both  is
  signal clk: bit := '1';
  signal x1, x2, x3, y1, y1s, y2, y2s, y3, y3s, y4, y4s: bit := '0';
  signal y1x, y2x, y3x, y4x: bit;
  signal x: bit_vector(1 to 3);
  signal y, ys: bit_vector(1 to 4);

  component fsm
    port (clk, x1, x2, x3: in bit;
         y1, y2, y3, y4: out bit );
  end component;

  for F1: fsm use entity work.fsm(bhv);
  for F2: fsm use entity work.fsm(str);

begin
  clk <= not clk after 50 ns;
  x <= x1 & x2 & x3;
  y <= y1 & y2 & y3 & y4;
  ys <= y1s & y2s & y3s & y4s;

  -- Test sequence
  process begin
    wait on clk until clk='0';
    x1<='0';                -- S1 -> S1
    wait on clk until clk='0';
    x1<='1';  x2<='1';      -- S1 -> S2
    wait on clk until clk='0';
    x3<='0';                -- S2 -> S3
    wait on clk until clk='0';
    x3<='0';                -- S3 -> S3
    wait on clk until clk='0';
    x3<='1';                -- S3 -> S1
    wait on clk until clk='0';
    x1<='1';  x2<='1';      -- S1 -> S2
    wait on clk until clk='0';
    x3<='1';                -- S2 -> S1
    wait on clk until clk='0';
    x1<='1';  x2<='0';      -- S1 -> S4
    wait on clk until clk='0';
    -- true                 -- S4 -> S1
  end process;

  F1: fsm port map (clk, x1, x2, x3, y1, y2, y3, y4);
  F2: fsm port map (clk, x1, x2, x3, y1s, y2s, y3s, y4s);

  y1x <= y1 xor y1s;  y2x <= y2 xor y2s;
  y3x <= y3 xor y3s;  y4x <= y4 xor y4s;

end architecture bench;