entity  fsm  is
  port ( clk, x1, x2, x3: in bit;
         y1, y2, y3, y4: out bit );
end entity fsm;

architecture  str  of  fsm  is
  signal q1, q2, j1, k1, j2, k2: bit;
  signal k1i, t1, y1b, y4b: bit;
  component jk_ff
    port ( clk, j, k: in bit;
           q, not_q: out bit );
    end component;
begin  --  bhv
  -- Next state and output functions
  j1 <= x2 and q2;
  k1i <= x1 and q1;    k1 <= not k1i;
  j2 <= not y1b;
  k2 <= '1';
  y1 <= y1b;    y1b <= q1 or q2;
  y2 <= not y4b;
  y3 <= j2;
  y4 <= y4b;    y4b <= t1 or j1 or k1i;    t1 <= x3 and j2;

  -- State register JK flip-flops
  FF1: jk_ff port map (clk, j1, k1, q1, open);
  FF2: jk_ff port map (clk, j2, k2, q2, open);
end architecture str;