entity  jk_ff  is
  port ( clk, j, k: in bit;
         q, not_q: out bit );
end entity jk_ff;
architecture  bhv  of jk_ff  is
  signal q_s: bit := '0';
begin
  process
    variable t: bit_vector(1 to 2);
  begin
    wait on clk until clk='1';
    t := j & k;
    case t is
    when "00" =>  null;
    when "01" =>  q_s <= '0';
    when "10" =>  q_s <= '1';
    when "11" =>  q_s <= not q_s;
    end case;
  end process;
  q <= q_s;    not_q <= not q_s;
end architecture bhv;