entity  d_ff  is
  port ( clk, d: in bit;
         q, not_q: out bit );
end entity d_ff;
architecture  bhv  of d_ff  is
  signal q_s: bit := '0';
begin
  process begin
    wait on clk until clk='1';
    q_s <= d;
  end process;
  q <= q_s;    not_q <= not q_s;
end architecture bhv;