Exams

Timeslots for exams

Up to 6 students per day. Registration is web-based in OIS.

Because the exam is oral, the following approximate times should be kept - at 12:00 the first two will start. After that, starting approximately from 12:30, one student may enter after every 10-20 minutes. The frequency will depend how many are there already in the room. The registration list may be used to define in which order the students enter (but it is optional).

This applies when we can meet face to face. Otherwise the exam will be done remotely (Skype etc) and exact times we'll agree separately. The exam is with open materials - you can use all information you can find when preparing answers.

Timeslots for office hours

Questions / Topics

1. Hardware description languages

  1. Hardware description languages - motivations and needs, different system level and hardware description languages.
  2. Simulation of digital systems. Different simulation models (unit, zero and delta delay).
  3. Synthesizable hardware description languages (VHDL, Verilog) - motivations and needs, limitations, sub-sets, etc.
  4. Verilog - behavioral, structural and mixed description styles. Differences from VHDL.
  5. Verilog - data types, simulation model and hierarchy. Differences from VHDL.
  6. SystemC - behavioral, structural and mixed description styles. Differences from VHDL.
  7. SystemC - data types, simulation model and hierarchy. Differences from VHDL.
  8. Simulation of continuous systems (SPICE, VHDL-AMS). Co-simulation of digital and analog systems.

2. Synthesis

  1. Design flow of digital systems. Levels of abstraction.
  2. Handling large projects when using hardware description languages. Test-bench design methodology.
  3. Physical, logic and register-transfer level syntheses.
  4. High-level synthesis, sub-tasks and methodology.
  5. Scheduling in high-level synthesis.
  6. Assignment and binding in high-level synthesis.
  7. Co-simulation - hardware/software co-simulation, co-simulation of different languages.
  8. Code transformations at system and algorithmic levels. Effects on hardware and software implementations.

When needed - results of hand-on exercises

Discussing elevator's and processor's architectures and coding styles. Discussing FIR filter's structure. 

Last modified 2020.04.21.